Security audit
Verilog Design Flow
Security checks for vulnerabilities and agentic risk
Overview
This is a coherent Verilog/SystemVerilog workflow helper that runs local simulation and waveform-analysis tools without hidden credential, network, persistence, or destructive behavior.
Install this only if you need Verilog/SystemVerilog design and simulation assistance. Review generated HDL and testbenches before running them, especially any $system calls, and install simulator/Python dependencies in a controlled environment.
Vulnerability Patterns
- Prompt InjectionInstruction Override, Hidden Instructions, Exfiltration Commands
- Data ExfiltrationExternal Transmission, Env Variable Harvesting, File System Enumeration
- Privilege EscalationExcessive Permissions, Sudo/Root Execution, Credential Access
- Supply ChainUnpinned Dependencies, External Script Fetching, Obfuscated Code
- Excessive AgencyUnrestricted Tool Access, Autonomous Decision Making, Scope Creep
Static analysis
No suspicious patterns detected.