Verilog Design Flow
v1.2.0Design, implement, and verify Verilog/SystemVerilog modules with spec-driven development, self-checking testbenches, and automated simulation workflows. Supp...
⭐ 0· 124·1 current·1 all-time
MIT-0
Download zip
LicenseMIT-0 · Free to use, modify, and redistribute. No attribution required.
Security Scan
Capability signals
These labels describe what authority the skill may exercise. They are separate from suspicious or malicious moderation verdicts.
OpenClaw
Benign
high confidencePurpose & Capability
Name/description (Verilog design, testbench, simulation, VCD analysis) align with what is included: SKILL.md guidance, a simulation wrapper (simulate.sh), and a VCD-checker (check_vcd.py). No unrelated environment variables, config paths, or obscure binaries are requested.
Instruction Scope
Runtime instructions stay within the stated domain: coding style, static check with slang, running a simulator (VCS/Xrun/iverilog), generating VCDs, and analyzing VCDs with the included Python script. The only external execution steps are expected (running simulators and python3). The SKILL.md references calling the bundled check_vcd.py from a post-simulation $system call — this is consistent with automated verification but means the testbench can invoke host commands, so run only trusted testbenches.
Install Mechanism
This is instruction-only with no install spec. That's low-risk, but the reference docs and script require the Python package 'vcdvcd' (pip) and external EDA simulators (VCS/Xrun/iverilog). Those dependencies are not installed automatically by the skill; the user must provide them. No downloads from external URLs or archive extraction are present.
Credentials
No required env vars, no credentials, and no config paths are requested. Scripts use locally available commands (vcs/xrun/iverilog/python3) and local files only. This is proportionate to a simulation workflow.
Persistence & Privilege
The skill does not request persistent or platform-wide privileges; always:false and no self-enablement steps are present. It does not modify other skills or system-wide agent settings.
Assessment
This skill appears coherent for Verilog simulation and VCD analysis, but take these precautions before running it: (1) Inspect testbench and RTL files you run — simulators and Verilog $system calls can execute host commands. The references show an example using $system("python3 check_vcd.py ...") which will run whatever Python is on the host. (2) Install runtime dependencies yourself (e.g., pip install vcdvcd in a virtualenv) and verify you have a trusted simulator. (3) Run simulations in a restricted/sandboxed environment if you’re running untrusted code. (4) The skill doesn’t auto-install packages or fetch remote code; if you see any attempt to download/execute from unknown URLs, treat that as suspicious.Like a lobster shell, security has layers — review code before you run it.
latestvk97a0w5q1n3nhmdkkrtycvrgp1846pqk
License
MIT-0
Free to use, modify, and redistribute. No attribution required.