{"skill":{"slug":"verilog-design","displayName":"Verilog Design Flow","summary":"Design, implement, and verify Verilog/SystemVerilog modules with spec-driven development, self-checking testbenches, and automated simulation workflows. Supp...","tags":{"latest":"1.2.0"},"stats":{"comments":0,"downloads":273,"installsAllTime":1,"installsCurrent":1,"stars":0,"versions":3},"createdAt":1774888172647,"updatedAt":1775331108870},"latestVersion":{"version":"1.2.0","createdAt":1775311545997,"changelog":"**Added static syntax checking with slang to enhance design reliability.**\n\n- Introduced a new phase for static syntax checking using slang before running simulations.\n- Updated design review checklist to require slang (0 errors) before simulation.\n- Clarified what slang checks for (syntax errors, type mismatches, undefined references, port errors, compliance).\n- Expanded tool support in the description and throughout documentation.\n- All existing flows remain; syntax check is an added mandatory step.","license":"MIT-0"},"metadata":null,"owner":{"handle":"billchen1020","userId":"s170h4mxdf1ydf98n4d2fh4szn83w60p","displayName":"billchen1020","image":"https://avatars.githubusercontent.com/u/185670692?v=4"},"moderation":null}